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MITSUBISHI SOUND PROCESSORS
M65827FP
10-TIMES SPEED CD-DSP
PACKAGE
FEATURES
*Normal speed to 8 times speed playback *Multi speed selector *Clock doubler *Error correction(C1:2 error correction,C2:4 error correction) *Channel control circuit ( Bilingual / swap / (L+R)/2) *Wide-band adjustment-free EFM-PLL *CLV gain control *Low power consumption and low radiation by 3.3V function of internal circuit
Outline 42P2R
APPLICATION
CD-ROM, CD-I, VIDEO-CD, etc.
0.8mm Pitch 450mil SSOP (8.4mm X 17.5mm X 2.0mm)
RECOMMENDED OPERATING CONDITIONS
Supply voltage range Rated voltage range 3.3V10% (internal logic,analog circuits,oscillation circuit) 5.0V10% (I/O buffer) 3.3V (internal logic,analog circuit) 5.0V (I/O buffer )
SYSTEM BLOCK DIAGRAM
Subcode Control PLL CLK OSC CLK SEL Digital Out Channel control DeEMP Subcode Digital Out
M
Motor Driver
Optical Pick-up
RF-AMP Pick-up Servo Auto Adjustment
PLL Slicer
EFM De-MOD
Interpolation
S E L
DATAOUT
PLL CLK OSC CLK 18kSRAM CLV Digital Servo MCU I/F Timing Generator (Speed Control) M65827FP
ECC C1:2errors C2:4errors
System Control Microprocessor
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BUILT IN FUNCTIONS Block name
Memory PLL
Description
*18 Kbit SRAM *8 frames jitter margin *Adjustment-free EFM-PLL *Wide-band lock range(1*8 times) *HF data slicer *EFM demodulator *Frame synchronization detection / protection / interpolation *Frame synchronization monitor *Subcode Q register *CRC checker *Subcode synchronous pattern detector (S0 and S1) *Emphasis flag detector and digital de-emphasis filter *Serial interface of subcode P~W (EIAJ CP-2401) *C1: 2 error correction, C2: 4 error correction (C1: 2 error correction, C2: 2 error correction selectable) *Unscramble / De-interleave *Error monitor *Average and pre-hold interpolation (for CD-DA mode ) *Interpolate prohibition (for CD-ROM mode ) *Mute control *Bilingual / swap / (L+R)/2 output *Lch / Rch independent attenuation control (256 steps) *Separate data output for CD-DA (DADT) and CD-ROM(ROMDT) *Based on EIAJ-1201 *C bit oscillation accuracy control *C bit source number control *PWM output *Low disc rotation detector *kick pulse control (256 steps) *Automatic brake control *CLV gain control *Master clock selector (Playback speed control) *Clock doubler *VCO clock selector *CLV servo control / mute control / attenuating level control *Configuration control *Attenuator control *Channel control *Play back speed control *Analog switch control *Error monitor control *Track counter control *Interrupt mask *Kick timer control *Digital audio interface C bit control *Reset / sleep / clock disable control *Subcode Q interface
EFM demodulation
Subcode control
Error correction
Interpolation DAC interface
Digital output
Digital CLV servo
Oscillation circuit
MCU interface
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PIN DESCRIPTION TABLE
Name VDD*VSS DVDD5 DVDD3 DVSS AVDD AVSS Clock XI XO C423 S846 S423 DXLPF DXRC PLL HFD IREF LPF RC HF HPF1 HPF2 TLC 11 13 15 16 17 18 19 20 I I I/O O I O O O HF defect signal input Current reference EFM-PLL loop filter connect pin EFM-PLL frequency gain control pin HF input High Pass Filter 1 High Pass Filter 2 Data slicer charge pump output DVDD5 AVDD AVDD AVDD AVDD AVDD AVDD AVDD 41 40 38 34 35 I O O O O Oscillator input Oscillator output Crystal half clock Crystal / PLL system clock Crystal / PLL half clock Clock doubler loop filter connect pin Clock doubler frequency gain control pin DVDD3 DVDD3 DVDD5 DVDD5 DVDD5 DVDD3 DVDD3 1 2 42 14 21 Digital power supply (5V power supply for I/O buffer) Digital power supply (3.3V power supply for internal circuit) Digital ground Analog power supply (3.3V power supply for analog circuit) Analog ground AVDD DVDD5 DVDD3 No. I/O Description Supply Schmitt Pull-Up
3 I/O 12 O
Data output * Digital Audio Interface DADT ROMDT LRCK DSCK DOTX 28 31 29 30 26 O O O O O Audio data output CD-ROM data output LR clock Data shift clock Digital audio interface output DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
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PIN DESCRIPTION TABLE (CONTINUED)
Name Subcode SBQS SCAND SBCO EFFK SCCK CRCF CLV PWM1 PWM2 33 32 O O Spindle motor PWM output (-) Spindle motor PWM output (+) DVDD5 DVDD5 5 22 23 24 25 27 O O O O I O Subcode Q interrupt signal Subcode sync. signal output (S0 and S1) Subcode data serial output PLL frame clock output Subcode data shift clock CRC flag output DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 No. I/O Description Supply Schmitt Pull-Up
Track counter TRIN INT 36 37 I O Track cross signal input Interrupting signal output DVDD5 DVDD5
MCU interface MCK R/W MSD MLA ALCR 6 7 8 9 10 I I I/O I I MCU shift clock input MCU data read / write control MCU data input / ouput MCU latch clock input Reset input DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
Monitor output EST LOCK/DRD 39 4 O O C1/C2 error flag output Lock monitor output / Low disc rotation detect signal output / Frame synchronization status (SYCLK) DVDD5 DVDD5
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NUMERICAL PIN LIST
Name DVDD5 DVDD3 DXLPF LOCK/DRD No. I/O 1 2 3 4 I/O O Description Digital power supply (5V power supply for I/O buffer) Digital power supply (3.3V power supply for internal circuits) Clock doubler loop filter connect pin Lock monitor output / Low disc rotation detect signal output / Frame synchronization status(SYCLK) Subcode interrupt signal output MCU shift clock input MCU data read / write control MCU data input / output MCU latch clock input Reset input HF defect signal input Clock doubler frequency gain control pin Current reference Analog power supply (3.3V power supply for analog circuits) I/O O I O O O EFM-PLL loop filter connect pin EFM-PLL frequency gain control pin HF input High Pass Filter 1 High Pass Filter 2 Data slice charge pump output Analog ground O O O I O O Subcode syncronization status (S0 and S1) Subcode data serial output PLL frame clock output Subcode readout clock Digital output CRC flag output DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 Supply Schmitt Pull-Up DVDD5 DVDD3 DVDD3 DVDD5
SBQS MCK R/W MSD MLA ALCR HFD DXRC IREF AVDD LPF RC HF HPF1 HPF2 TLC AVSS SCAND SBCO EFFK SCCK DOTX CRCF
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
O I I I/O I I I O I
DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD3 AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD
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NUMERICAL PIN LIST (CONTINUED)
Name DADT LRCK DSCK ROMDT PWM2 PWM1 S846 S423 TRIN INT C423 EST XO XI DVSS No. I/O 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 O O O O O O O O I O O O O I Description Audio data output LR clock Data shift clock CD-ROM data output Spindle motor PWM output (+signal) Spindle motor PWM output (-signal) Crystal / PLL system clock Crystal / PLL half clock Track cross signal input Interrupt signal output Crystal half clock C2/C1 error output Oscillator output Oscillator input Digital ground Supply Schmitt Pull-Up DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD3 DVDD3
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PIN CONFIGURATION
DVDD5 DVDD3 DXLPF LOCK/DRD SBQS MCK R/W MSD MLA ALCR HFD DXRC IREF AVDD LPF RC HF HPF1 HPF2 TLC AVSS
1 2 3 4 5 6 7 8
42 DVSS 41 XI 40 XO 39 EST 38 C423 37 INT 36 TRIN 35 S423
M65827FP
9 10 11 12 13 14 15 16 17 18 19 20 21
34 S846 33 PWM1 32 PWM2 31 ROMDT 30 DSCK 29 LRCK 28 DADT 27 CRCF 26 DOTX 25 SCCK 24 EFFK 23 SBCO 22 SCAND
OUTLINE : 42P2R (Top view)
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RC
CRCF
SBQS
DVSS
DVDD5
DVDD3
SCCK
SBCO
SCAND LOCK/DRD
LPF
HFD
AVDD VCO HF Defect Control Sub Code Serial I/F CRC Checker CIRC Decoder Correction Control SYNC Detector EFM De-Modulator EFM Interpolation Address Generator 18Kbit SRAM Flag Control System Clock Selector Timing Generator De-EMP Digital Audio Interface PWM Micro Computer I/F Track Counter
S E L
PLL
AVSS NRZ PLL
SEL
Syndrome Register
BLOCK DIAGRAM
HF Sub Code Sync Det. SUBQ Register
Slicer
HPF1
CIRC Sequencer ECC MCU I/F DAC I/F
HPF2
TLC
Current Control
IREF
Flag Control
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Clock Doubler 2/3 Det. CLV Control CLV INT R/W MLA MSD MCK S846 S423 C423 DOTX PWM1 PWM2
EFFK
EFM Timing Generator SYNC Protector
Channel Control
S E L
MITSUBISHI ELECTRIC
Timing Generator
Attenuate Control
XI
Oscillator
S E L
XO
DXLPF
S E L
DXRC
Freq. Det.
DAC I/F
+
Fig 1 : Block diagram
Phase Det.
EST
TRIN
LRCK
ALCR
DADT
DSCK
ROMDT
ABSOLUTE MAXIMUM RATING
(Ta=25C unless otherwise noted) Symbol DVDD5-DVSS DVDD3-DVSS AVDD-AVSS Vi Vo Pd Topr Tstg Parameter Power supply voltage Power supply voltage Power supply voltage Input voltage Output voltage Power consumption Ambient temperature Storage temperature Condition Limit -0.3 ~+7 -0.3 ~+4.5 -0.3 ~+4.5 VSS-0.3ViVDD+0.3 VSSVoVDD 600 -10 ~+70 -40 ~+125 Unit V V V V V mW C C
RECOMMENDED OPERATING CONDITIONS
Symbol DVDD5 DVDD3 AVDD VIH VIL Parameter 5V digital power supply voltage 3.3V digital power supply voltage Analog supply voltage "H" output voltage "L" input voltage Oscillation frequency (X'tal) Single speed Double speed Quad speed 6 times speed 8 times speed Condition MIN 3.0 3.0 3.0 0.7DVDD DVSS 8.4672 16.9344 33.8688 50.8032 67.7376 8.6436 17.2872 34.5744 51.8616 69.1488 Limit TYP 5.0 3.3 3.3 MAX 5.5 3.6 3.6 DVDD5 0.3DVDD V V V V V MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Unit
fOSC
fVCO
Oscillation frequency (VCO)
Single speed Double speed Quad speed 6 times speed 8 times speed
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ELECTRICAL CHARACTERISTICS
(Ta=25C,DVDD5=5V, DVDD3=3.3V, AVDD=3.3V unless otherwise noted) Symbol Parameter Condition MIN DVDD5 Operating voltage (5V, digital) Ta=-10~+70C 8X 8X~10X AVDD Operating voltage (3.3V, analog) Ta=-10~+70C 8X 8X~10X | DD Operating current f osc=8.4672MHz f vco=8.6436MHz VDD=4.5V,| OH=-0.8mA VDD=4.5V,| OL=0.8mA VIH=4.5V VIL=0.5V 3.5 0.4 2 -2 2 -2 3.0 3.0 3.2 3.0 3.2 Limit TYP 5.0 3.3 3.3 3.3 3.3 20 MAX 5.5 3.6 3.6 3.6 3.6 50 V V V V V mA V V A A A A kHz kHz kHz kHz kHz kHz 25 50 100 k Unit
DVDD3 Operating voltage (3.3V, digital) Ta=-10~+70C
| OH | OL | IH | IL | OZH | OZL f PLL1 f PLL2 f PLL3 f DX1 f DX2 f DX3 Rpu
"H" output voltage "L" output voltage "H" input current "L" input current
Off condition "H" output current VOH=4.5V Off condition "L" output current VOL=0.5V VCO (EFFK) free run frequency (RIREF=110k,RRC=91k) VLPF=1.0V VLPF=1.5V VLPF=3.0V Clock Doubler (S423) free run VLPF=1.0V frequency VLPF=1.5V (RIREF=110k,RRC=91k) VLPF=3.0V Pull up resistance
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DETAILED DESCRIPTION
1. MCU interface (1)Connection MSD MCK M65827FP MLA B/W MCU
Pin No. 8 6 9 7
Signal name MSD MCK MLA R/W
Contents MCU serial data input output pin MCU shift clock input pin MCU data latch clock input pin Data read write control pin (H : Read, L : Write)
I/O I/O I I I
(2)Mode description
Address No.
Address A7 L L L L L L L L L L L L L L L L H A6 A5 L L L L L L L L L L L L L L L L X L L L L L L L L L L L L L L L L X A4 L L L L L L L L L L L L L L L L X A3 A2 L L L L L L L L H H H H H H H H X L L L L H H H H L L L L H H H H X A1 L L H H L L H H L L H H L L H H X A0 L H L H L H L H L H L H L H L H X
Data control CLV servo, ATT, mute control Configuration Attenuation (Lch) control Attenuation (Rch) control Channel control Playback speed control Analog switch control Monitor output select Track counter (LSB) Track counter (MSB) Track counter interrupt value (LSB) Track counter interrupt value (MSB) Interrupt mask Kick timer Digital audio interface C bit control Reset / Sleep / Clock disable control Test Mode (For shipping test mode)
0 1 2 3 4 5 6 7 8 9 A B C D E F 80
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(3)Write timing When R/W pin is L, MCU I/F is set in write mode. Address(1st byte) and data(2nd byte) are input with LSB first. Address and data are captured at the rising edge of MCK and are latched in internal register at the rising edge of MLA. R/W LSB MSD MCK MLA t6 t1 t2 t5 t3 t4 Symbol t1 t2 t3 t4 t5 t6 t7 Term Shift clock pulse width Shift clock set up time Shift clock hold time Latch clock set up time Latch clock pulse width Write set up time Write hold time Min 200 100 100 200 200 250 200 Unit nsec nsec nsec nsec nsec nsec nsec t7
A0 A1 L
Address(1st byte)
A2 A3 A4 A5 A6
MSB
A7
LSB
D0 D1 D2
Data(2nd byte)
D3 D4 D5 D6
MSB
D7
(4)Read timing (Subcode Q register interface) When R/W pin is H, MCU I/F is set in subcode Q register read mode. Subcode Q data output from MSD pin at the falling edge of MCK. Refer to (6) subcode Q I/F .
H
R/W MSD MCK t9 t8 t10
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q78 Q77 Q76 Q75 Q74 Q73 Q72
Symbol t8 t9 t10
Term Shift clock pulse width Read set up time Read hold time
Min 200 250 400
Unit nsec nsec nsec
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(5) Write mode
Address 00h
Register name D0 Reserved D1 S/S D2 BCON D3 BRAK D4 ATT D5 MUTE D6 TRST D7 Reserved
CLV servo, Mute / ATT control 0 1 Default
CLV OFF (STOP) Automatic brake mode Manual brake OFF ATT OFF MUTE ON Kick timer on
CLV ON (START) Manual brake mode Manual brake ON ATT ON MUTE OFF Kick timer off
0 0 1 0 0 1
D0: Reserved Don't care. D1: S / S (Start / Stop) D2: BCON (Automatic brake control) D3: BRAK (Brake) (1) Disc start When S/S register changes from "0" to "1" , the kick pulse that is set by the kick control register at address 0Bh is output. After kick mode, disc rotation switched to CLV mode automatically. S/S PWM1 (-Signal) PWM2 (+Signal) CLV OFF (2) Disc stop (2-1) BCON=0 (Automatic brake mode) When S/S register changes from "1" to "0", the brake pulse that is calculated by the internal circuit output for the time 3t automatically. After brake mode, PWM switches to CLV off mode. The time t is defined as the time that internal circuit detect the 2/3 rotation after S/S register changes 0. The time of detecting the 2/3 rotation can be monitored by DRD signal in LOCK/DRD pin. S/S PWM1 (-Signal) PWM2 (+Signal) CLV ON t 2t CLV OFF tmax = 8.8 sec Detect 2/3 rotation Kick time* CLV ON *Kick timer can be controlled by kick control register.
BRAKE (26.4sec max.)
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(2-2) BCON=1 (Manual brake mode) When S/S register change from "1" to "0", PWM output brake pulse while BRAK register is "1". This mode is used to stop the disc rotation by manual operation. S/S PWM1 (-Signal) PWM2 (+Signal) BRAK CLV ON D4: ATT (Attenuate) ATT=0: Attenuation OFF ATT=1: The output data of DADT and ROMDT are attenuated by address 02h and 03h. D5: MUTE MUTE=0: Mute on for DADT and ROMDT. MUTE=1: Mute off for DADT and ROMDT. D6: TRST (kick timer reset) TRST=0: Kick timer active TRST=1: Kick timer stopped D7: Reserved Don't care BRAKE CLV OFF
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Address 01h
Register name
Configuration 0 Interpolation enable (Audio mode) C1:2 errors correction C2:4 errors correction False-lock protection circuit On VCO upper limiter OFF HFD enable Normal CLV gain mode 1/2 CLV gain mode 1 Interpolation disable (CD-ROM mode) C1:2 errors correction C2:2 errors correction Quasi-lock protection circuit Off VCO upper limiter ON HFD disable CLV gain select mode 1/4 CLV gain mode Inhibit Default 0 0
D0 NONAUDIO D1 ECCMOD
D2 FLPDIS D3 PFHEN D4 HFDDIS D5 GAINCNT D6 GAINSEL D7 Reserved D0: NONAUDIO
0 0 0 0 0 0
NONAUDIO=0: Interpolation is enabled C2 flag from EST pin output at 16 bit audioword unit. NONAUDIO=1: Interpolation is disabled, prohibit interpolation. C2 flag from EST pin output at 8 bit data byte unit. D1: ECCMOD (Error correction mode) ECCMOD=0: C1:2 error correction,C2:4 errors correction ECCMOD=1: C1:2 error correction,C2:2 errors correction D2: FLPDIS (False lock protection circuit disable) FLPDIS=0: False lock protection circuit on FLPDIS=1: False lock protection circuit off (Refer to address 07h) D3: PFHEN (VCO oscillation frequency upper limiter enable) PFHEN=0: VCO oscillation frequency limiter is stopped PFHEN=1: VCO oscillation frequency limiter is active Limiter value = 8.6436MHz X 1.3 X S (S:Playback speed) D4: HFDDIS (HFD disable) HFDDIS=0: HFD input enable HFDDIS=1: HFD input disable D5:GAINCNT(CLV gain control) D6:GAINSEL(CLV gain select) GAINCNT=0: Normal gain mode. GAINCNT=1: CLV gain control mode. CLV gain can be selected 1/2 and 1/4 of normal gain by GAINSEL register.
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(a) Normal CLV gain mode (GAINCNT=0) PWM2 PWM1 (b) 1/2 CLV gain mode (GAINCNT=1,GAINSEL=0) PWM2 PWM1 CLV Mode PWM1=PWM2 CLV Mode PWM1=PWM2 CLV Mode
(c) 1/4 CLV gain mode (GAINCNT=1,GAINSEL=1) PWM2 PWM1 CLV Mode PWM1=PWM2 PWM1=PWM2 PWM1=PWM2 CLV Mode
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Address 02h / 03h
MSB Address 02h 03h Default D7 D6 L7 L6 R7 R6 0 1
7 n=0
Attenuation level control LSB D5 L5 R5 0 D4 D3 D2 D1 D0 L4 L3 L2 L1 L0 R4 R3 R2 R1 R0 0 0 0 0 0
7 n=0
Coefficience Attenuation Default value
Lcoe=
Ln X2
-(8-n)
Rcoe=
Rn X2
-(8-n)
LATT=20 X LOG(Lcoe) LATT=RATT= -12dB
RATT=20 X LOG(Rcoe)
When ATT register at address 00h is set to "1", the output data from DADT and ROMDT are attenuated by the attenuation level control register.
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Address 04h
Register name D0 D1 D2 D3 D4 D5 D6 D7 CC1 CC2 CC3 CC3 DACIF DDEPASS SFLD AUTOLD
Channel control 0 1 Default 1 0 0 1 DAC interface mode 0 Automatic de-emphasis mode Software load on Automatic load off DAC interface mode 1 De-emphasis pass mode Software load off Automatic load on 0 0 1 1
Channel control register (Refer to Table 1)
D0: CC0 (Channel control 0) D1: CC1 (Channel control 1) D2: CC2 (Channel control 2) D3: CC3 (Channel control 3) Table 1 : Channel control table CC3 L L L L L L L L H H H H H H H H CC2 L L L L H H H H L L L L H H H H CC1 L L H H L L H H L L H H L L H H CC0 L H L H L H L H L H L H L H L H Lch output MUTE MUTE MUTE MUTE R R R R L L L L (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2 Rch output MUTE R L (L+R)/2 MUTE R L (L+R)/2 MUTE R L (L+R)/2 MUTE R L (L+R)/2 MONAURAL STEREO SWAP Note MUTE
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D4: DACIF (DAC interface) (1) DACIF=0 (DAC interface mode 0) When LRCK is "H", Lch is selected LRCK DSCK DADT ROMDT EST
NONAUDIO=0
0
MSB Lch (Upper)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MSB
NONAUDIO=1
Lch (Lower) Upper + Lower
EST (2) DACIF=1 (DAC interface mode 1) LRCK DSCK DADT MSB ROMDT
NONAUDIO=1
When LRCK is "H", Lch is selected
15 14 13 12 11 10 9 Lch (Upper)
8
7
6
5
4
3
2
1
0 Lch (Lower)
MSB
EST
NONAUDIO=0
EST
Upper + Lower
D5: DDEPASS (Digital de-emphasis pass) DDEPASS = 0 : When emphasis flag is detected, internal digital de-emphasis circuit work automatically. DDEPASS = 1 : Internal digital de-emphasis pass mode. D6: SFLD (Software Load) SFLD = 0 : When PLCKSEL register is 1, the EFM address counter is set the value that has 8 frames jitter margin. SFLD = 1 : EFM address counter is not influenced by this resister D7: AUTOLD (Automatic Load) AUTOLD = 0 : EFM address counter is not influenced by lock status. AUTOLD = 1 :When PLCKSEL register is 1, the EFM address counter is set the value that has 8 frames jitter margin at the LOCK point.
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Address 05h
Register name D0 D1 D2 D3 D4 D5 D6 D7 PLCKSEL CKSEL0 CKSEL1 CKSEL2 PLSEL0 PLSEL1 DXSEL DX24SEL
Play back speed selector 0 1 PLL mode Default 0 0 0 0
Xtal mode Master clock selector (Refer to Table 2)
PLL clock selector (Refer to Table 3) Clock doubler not select X2 Clock doubler select X4
0 0 0 0
D0: PLCKSEL (PLCK select) PLCKSEL=0: ECC circuit is worked by Xtal clock. PLCKSEL=1: ECC circuit is worked by PLL clock. D1: CKSEL0 (Clock select) D2: CKSEL1 (Clock select) D3: CKSEL2 (Clock select) CKSEL2 CKSEL1 CKSEL0 L L L L H H H H L L H H L L H H L H L H L H L H Divide ratio 1 1/2 1/3 1/4 1/6 1/8 1/10 1/12 Table 2: Master clock selector
D4: PLSEL0 (PLL clock select) D5: PLSEL1 (PLL clock select) PLSEL1 PLSEL0 L L H H L H L H Divide ratio 1 1/2 1/4 1/8 Playback speed * Don't use 8X 2X,4X 1X Table 3: PLL clock selector * Recommend value
D6: DXSEL (Clock doubler select) DXSEL=0: Clock doubler does not select DXSEL=1: Clock doubler select D7: DX24SEL (Clock doubler 24 select) DX24SEL=0: Double clock of Xtal is generated. DX24SEL=1: Quad clock of Xtal is generated. MITSUBISHI ELECTRIC
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Address 06h
Register name D0 D1 D2 D3 D4 D5 D6 D7 IREF Reserved HPF1 HPF2 Reserved Reserved Reserved Reserved
Analog switch control 0 OFF 1 ON Default 1
OFF OFF
ON ON
0 0
D0: IREF (Current reference control resistance select ) Table 4: Current reference control IREF L H Sleep Current reference supply ON
Function
RIREF
IREF
Current Reference Supply
IREF=L: The analog block change to sleep mode by stopping the reference current to analog circuit. Almost analog circuit stop the function, but the internal VCO does not stop the oscillation. Because the loop filter can not discharge. If VCO need to stop the oscillation in the sleep mode, please send the command ( address:CEh, data:01h EFM-PLL charge pump output "L" ) LSI change to low power supply mode by using the analog sleep mode and the digital sleep mode. IREF=H: Set the reference current to analog circuit by the external resistor. D2: HPF1 (HPF select 1) D3: HPF2 (HPF select 2) Table 5: High Pass Filter HPF2 L L H H HPF1 L H L H External resistance value
CHF
HF
HF Comparator
RTLC0 RTLC0 RTLC0 || RTLC2 RTLC0 || RTLC1 || RTLC2
TLC HPF1 HPF2 TLC Charge Pump
These resisters are used to control the cut off frequency of the high pass filter that is composed by CHF and RTLC. This high pass filter is used to reject the defect ( Example: Finger print )that can not be detected by the HF defect signal from SERVO IC.
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RTLC1 RTLC2
RTLC0 || RTLC1
PLAYBACK SPEED / ANALOG SWITCH CONTROL BLOCK DIAGRAM
CKSEL0~2 1/2 X2 / X4 Clock Doubler 1/2 DXSEL 1/8 1/10 DXLPF DXRC 1/12 ECC 1/3 1/4 1/6 PLCKSEL CLV
XI
XO
CDX1
C423
CDX2 RDX
RDXRC
S423 S846 HF
1/2 588 576 3T Detector
CHF
HF signal
RTLC0
RTLC1 RTLC2
HF Comp. HPF2 HPF1
11T Detector
Frequency Comparator Phase Comparator NRZ EFM
TLC
CTLC C RLPF
LPF
Charge Pump
Charge Pump
PLSEL0~1
CLPF
Charge Pump VCO 1/2 1/2 1/2 EFM
RRC
RC
From Servo IC HFD Current reference Supply LPF TLC VCO
RIREF
IREF
Fig. 2: Playback speed control / analog switch control block diagram MITSUBISHI ELECTRIC
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Address 07h
Register name D0 ERM0 D1 ERM1 D2 ERM2 D3 LOCKSEL0 D4 LOCKSEL1 D5 LOCKMOD D6 FLSEL0 D7 FLSEL1
Monitor control 0 Error monitor select (Refer to Table6 ) 1 Default 0 0 0 Lock monitor select (Refer to Table7) Ignore disc rotation Depend on disc rotation 0 0 0 0 0
False-lock protection clock duty select register (Refer to Table8)
D0: ERM0 (Error monitor select 0) D1: ERM1 (Error monitor select 1) D2: ERM2 (Error monitor select 2) Table 6: Error monitor output (a) 4 error correction mode ERM2 ERM1 ERM0 EST output(error monitor) L L L L H H H H L L H H L L H H L H L H L H L H C1,C2 decoder discorrectable
C2 decoder detects more than 4 errors C2 decoder detects more than 3 errors C2 decoder detects more than 2 errors C2 decoder detects more than 1 errors C1 decoder detects more than 3 errors C1 decoder detects more than 2 errors C1 decoder detects more than 1 errors
(b) 2 error correction mode ERM2 ERM1 ERM0 L L L L H H H H L L H H L L H H L H L H L H L H EST output(error monitor) C1,C2 decoder discorrectable Disable Disable
C2 decoder detects more than 2 errors C2 decoder detects more than 1 errors C1 decoder detects more than 3 errors C1 decoder detects more than 2 errors C1 decoder detects more than 1 errors
When ERM0, ERM1 and ERM0 are all "L", the error signal synchronize with the data from the DADT and ROMDT pins. The other mode can be used as an error monitor. D3: LOCKSEL0 (Lock monitor select 1) D4: LOCKSEL1 (Lock monitor select 0) Table 7: LOCK/DRD output
LOCK SEL1 LOCK SEL0
LOCK/DRD output LOCK/DRD SYCLK LOCK DRD
Description BRAK register=0: LOCK monitor BRAK register=1: DRD output Frame LOCK status output (H: Lock, L: Unlock) LOCK monitor output (H: Lock, L: Unlock) Low disc rotation detect (H: Less than 2/3, L: More than 2/3) MITSUBISHI ELECTRIC
L
L
L H H
H L H
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D5: LOCKMOD (Lock mode) LOCKMOD=0: Independent of disc rotation, LOCK/DRD becomes "H" when PLL are locked in frame /16 unit. LOCKMOD=1: LOCK/DRD becomes "H" when disc rotation gets close to target, perform CLV mode and PLL are locked in frame /16 unit.
Accelerating Disc rotation LOCK/DRD S/S=0 1
CLV state
When LOCKMOD is 1, after PLL are locked in frame/16 unit and disc rotation is CLV mode, LOCK/DRD outputs "H" .
When LOCKMOD is 0 and PLL are locked in frame/16 unit, LOCK/DRD outputs "H" . D6: FLSEL0 (False-lock protection clock duty control register 0) D7: FLSEL1 (False-lock protection clock duty control register 1) Table 8: False-lock protection clock duty control register FLSEL1 L L H H FLSEL0 L H L H Duty 1/4 1/8 1/16 1/32 Duty =
tFL2 tFL1 tFL1 tFL1 + tFL2 tFL1 + tFL2 = 557msec X (1/S)
(S:Playback speed)
When mute data continue for a long time, PLL sometimes become hard to lock up. When the FLPDIS register at address 01h is "L", false-lock protection circuit adds stimulation to VCO control terminal which causes the PLL to lock up. False-lock protection circuit operates while false-lock protection clock is "L" (tFL1) to increase VCO oscillation frequency. This effect can be selected by the FLSEL1,0 register. This action can be stopped by the FLPDIS register at address 01h.
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Address 08h / 09h
MSB Address 08 h (LSB) 09 h (MSB) Track counter value=
15 n=0
Track counter control LSB
D7 D6 D5 D4 D3 D2 D2 D1 T7 T6 T5 T4 T3 T2 T1 T0 T15 T14 T13 T12 T11 T10 T9 T8
Default = 0000h
Tn X2n
Up to 2^16 track cross signals can be counted by the internal track corss counter. After the target track cross number is set in the register by 2 byte data, the track cross counter is counted down at the rising edge of the track cross signal from servo LSI. Three kinds of the counter status can be output as the interrupt signal from INT pin by the interrupt mask register at address 0Ch.
Track counter set COUNTER TRIN INT Optional value by 1/2 of target track cross setting address 0Ah and 2Bh register
N N-1 N-2 m m-1 1/2N 1/2N-1 1/4N 1/4N-1
N:Target track cross number
2 1 0
Count complete
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Address 0Ah / 0Bh
MSB Address 08 h (LSB) 09 h (MSB)
Track counter interrupt value control LSB
D7 D6 D5 D4 D3 D2 D2 D1 CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 CT15CT14 CT13 CT12CT11 CT10 CT9 CT8
15 n=0
Default = 0000h
Track counter interrupt value =
CTn X2n
An optional interrupt value can be set by 2 byte in the track counter interrupt register. Interrupt signal outputs from INT pin. It can be prohibited by interrupt mask register at address 0Ch.
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Address 0Ch
Register name D0 JPEND D1 JPHAF D2 JPCMP D3 TRINO D4 MOVF D5 CLVDOWM D6 CLVUP D7 Reserved
Interrupt mask
0
1
Default 0 0 0 0 0 0 0 0
No interrupt mode Interrupt mode when track counter reches 0 No interrupt mode Interrupt mode when track counter reches 1/2 of set value No interrupt mode Interrupt mode Interrupt mode when track counter reches the optional set value at address 0Ah and 0Bh Track cross signal output to INT pin directly
No interrupt mode Interrupt mode when over 8 frames jitter margin Rough servo off Rough servo off 0 Rough servo on (- ) Rough servo on (+) Prohibit
D0: JPEND (Jump to end) D1: JPHAF (Jump to half) D2: JPCMP (Jump to comp) When JPEND register is 1, the interrupt signal that output at counter reaches 0 is masked. When JPHAF register is 1, the interrupt signal that output at counter reaches 1/2 of target track jump number is masked. When JPCMP register is 1, the interrupt signal that output at counter reaches value of interrupt register at address 0Ah/0Bh is masked. Track counter set N:Target track jump number Counter Value TRIN ttc INT changed to "H" at track counter setting D3: TRINO (TRIN out) JPCMP JPHAF . ttc=1/ftc . ftc=track cross frequency L;hold JPEND
N N-1 N-2 m m-1 1/2N 1/2N-1 1/4N 1/4N-1 2 1 0
TRINO=0: Interrupt signal which is set by D0~D2,D4 outputs to INT pin. TRINO=1: Track cross signal input on the TRIN pin outputs to INT pin. At this time, the interrupt signal set by D0~D2,D4 is not be output. D4: MOVF (Memory Over Flow) MOVF=0: interrupt signal doesn't be generated. MOVF=1: interrupt signal, which is generated when memory overflows exceeds 8 frames of jitter margin, is masked. Interrupt signal becomes "L" when 8 frames are detected and returns "H" after 128 frames pass. 8 frames detection INT 128 frames 1 frames = 136 / S sec MITSUBISHI ELECTRIC S:Playback speed (S times)
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D5: SPMDOWN (Spindle motor down) D6: SPMUP (Spindle motor up) Rough servo mode can be realized by CLVDOWN and CLVUP register. Table 9. Rough servo mode SPMUP L L H H SPMDOWN L H L H H L L H PWM1(-) PWM2(+) Description Normal mode Rough servo (-) mode Rough servo (+) mode Prohibit
D7:Reserved Set "0" in this register. Command advantage about CLV servo is as follows. Rough servo mode > Automatic CLV mode > CLV disable mode (Address 0Ch) (Address 00h) (Address 0Ch)
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Address 0Dh
Kick timer control MSB LSB D2 S2 D2 D1 S1 S0 Default = 20h
Address 0Dh
D7 D6 D5 D4 D3 S7 S6 S5 S4 S3
256 kinds of Kick pulse time can be set by 8 bit data. Kick time is calculated as follows:
7 n=0 n
N=
Kick Time
Tn X2
S : Playback speed
Tkick =8.71 msec X N X (1/S)
Register of initial state are set to 20h (=32), kick time at single speed (S=1) is as follows:
Tkick =8.71 msec X 32 X (1/1) =278.72 msec.
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Address 0Eh
Register name D0 ACCK0 D1 ACCK1 D2 SOURCE0 D3 SOURCE1 D4 SOURCE2 D5 SOURCE3 D6 DAOSEL D7 Reserved
Digital audio interface C bit control
0 Bit 28 of Cbit set to 0. Bit 29 of Cbit set to 0. Bit 16 of Cbit set to 0. Bit 17 of Cbit set to 0. Bit 18 of Cbit set to 0. Bit 19 of Cbit set to 0. After channel control
1 Bit 28 of Cbit set to 1. Bit 29 of Cbit set to 1. Bit 16 of Cbit set to 1. Bit 17 of Cbit set to 1. Bit 18 of Cbit set to 1. Bit 19 of Cbit set to 1. Before channel control
Default 0 0 0 0 0 0 0
D0: ACCK0 (Crystal accuracy control 0) D1: ACCK1 (Crystal accuracy control 1) ACCK1 0 0 1 1 D2: SOURCE0 D3: SOURCE1 D4: SOURCE2 D5: SOURCE3 ACCK0 0 1 0 1 (Source (Source (Source (Source Description Level || Level ||| Level | Prohibited NO.0) NO.1) NO.2) NO.3) Description Default Source NO.1 Source NO.2 Source NO.3 Table 9 : Crystal accuracy control
SOURCE3 SOURCE2 SOURCE1 SOURCE0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1
1
1
1
1
Source NO.16 Table 10: Source No. control
D6: DAOSEL (Digital audio interface select)
DAOSEL=0: Digital out is influenced by channel control and attenuation circuit. DAOSEL=1: Digital out is not influenced by channel control and attenuation circuit.
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Address 0Fh
Register name D0 SRST D1 HRST D2 SLP D3 TXDIS D4 C4DIS D5 S8DIS D6 S4DIS D7 APC EN
Soft reset / sleep / clock disable control
0 Soft reset OFF Hard reset OFF Sleep OFF Digital output ON C432 ON S846 ON S423 ON APC OFF (PLCKSEL=1) Soft reset ON Hard reset ON Sleep ON Digital output OFF S423 OFF S846 OFF C432 OFF
1
Default 0 0 0 0 0 0 0 0
APC ON (PLCKSEL=1)
D0: SRST (Soft reset) SRST=0: Soft reset OFF SRST=1: Default value are set in the write register by soft reset. This register returns to "0" after soft reset. D1: HRST (Hard reset) HRST=0: Hard reset OFF HRST=1: LSI resets are carried out. Reset state continued while HRST register is "1". Reset is canceled by sending "0" to HRST register. D2: SLP (Sleep) SLP=0: Sleep OFF SLP=1: Internal RAM and digital circuits can be put into sleep mode to reduce power consumption while the LSI is not in use. Sleep mode can be canceled by external reset or hard reset using the HRST register. Using address 06h, the analog circuits can also be put into sleep mode D3: TXDIS (Digital out disable) TXDIS=0: Digital out data output from DOTX pin. TXDIS=1: Digital out disabled and DOTX fixed to "L" D4: C4DIS (C423 disable) C4DIS=0: Crystal system clock output from C423 pin C4DIS=1: C423 pin disabled and fixed to "L" D5: S8DIS (S846 disable) S8DIS=0: S846 pin output crystal or PLL master clock. S8DIS=1: S846 pin disabled and fixed to "L" D6: S4DIS (S423disable) S4DIS=0: S423 pin output crystal or PLL system clock. S4DIS=1: S423 pin disabled and fixed to "L" D7: APC EN (APC ENABLE) APCEN=0: Automatic phase control circuit in CLV servo is disabled APCEN=1: Automatic phase control circuit in CLV servo is enabled When PLCKSEL register is "1", APCEN register influence APC function When PLCKSEL register is "0", APCEN register is ignored. MITSUBISHI ELECTRIC
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(6) Read mode
Subcode Q I/F H B1 B2 B3 B4 B5 B6 B7 B8 B9 BA
R/W MSD SBQS 75 Hz typ
(Reading completion<10msec recommended) MSD MCK Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 15 14 13 12 11 10 Q9 Q8
LSB
1 Bite
MSB
Subcode Q data which is stored in internal 80 bit register can be read in serial clock of MCU. When R / W signal is "H", MSD are settled to output. By inputting 80 ck to MCK pin between two rising edges of SBQS pin, MSD pin output subcode Q data at the falling edge of MCK. Subcode Q data are output reversed MSB, LSB in 8 bit unit. SBQS pin output "L", when next condition are satisfied and internal register can be read.
a)CRC flag is OK. b)Subcode synchronization signals S0,S1 are both detected at fixed position. (S0 AND S1) When conditions a) and b) are both satisfied, SBQS pin outputs "L". SBQS outputs 75Hz typ (=13.3msec) at single speed playback. In the case of S-times speed playback, it outputs S x 75Hz (13.3msec / S) so please notice when MCU design. Subcode Q register is valid from the rising edge of SQBS to the next rising edge. For actual design, please read subcode Q. (Normal speed playback: recommend less than 10msec readout completion)
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2.Subcode interface Among the data which are converted from 14 bits EFM signals to 8 bits symbols, subcode P,Q,R,S,T,U,V and W are output from SBCO pin by inputting a shift clock to SCCK pin. If input frequency to SCCK is more than 8ck, SBCO becomes "L". S0 SUBCODE FRAME EFFK SCAND S0,S1:SUBCODE SYNC S1 SF3 SF4 SF5 S0 S1
SF97 SF0 SF1 SF2
SF96 SF97 SF0 SF1 SF2
SBCO SCCK EFFK
P
Q
R
S
T
U
V
W
L
Subcode data synchronization status SCAND outputs "H" only when subcode synchronization patterns both S0 and S1 (S0 AND S1) are detected within a both fixed area of internal synchronization protection circuit. Subcode Q CRC check outputs to CRCF pin. When CRC is OK, CRCF changes to "H", when CRC is NG, CRCF becomes "L". SCAND CRCF CRC OK CRC NG CRC OK
Correspondence with EIAJ CP-2401 are as follows: M65827FP SCAND EFFK SCCK SBCO CP-2401 SBSY SFSY CLCK DATA Signal variation Subcode block synchronization Subcode frame synchronization Shift clock Output data
Table 11: Subcode serial interface corresponding table
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3.EFM-PLL CIRCUIT (1) Data slicing / PLL The M65827FP has an analog front-end for incoming HF(EFM) signal. Using CMOS - Analog technology, the front - end is comprised of an automatic slice level control circuit and EFM-PLL circuit with internal adjust - free VCO. Under figure shows a block - diagram of the analog front - end. The HF signal is sliced by the HF comparator and a DC level is fed back from TLC to HF through some the external CR. If HFD becomes "H" because of defect in disc, then TLC becomes off state and holds the DC level. EFM - PLL is for extracting the EFM clock signal from the HF signal. The PLL circuit has a phase / frequency comparator so the M65827FP has a wide capture / lock range and there is no need to adjust the VCO. LPF is the charge-pump output and same-time control voltage input to the VCO.LPF becomes off state if HFD becomes "H". M65827FP has an analog switch which it exchanges the analog external constants for playback speed (Refer to address 06h). When VCO frequency is higher than 1.3 of target frequency, high frequency limiter suppress VCO frequency. High frequency limiter can be disabled by D3 bit of address 01h. Low frequency limiter is used for not stopping VCO oscillation; it can not be controlled this from the outside. Sync loss counter becomes active when synchronization signal can't be detected, prevent from carrying out frequency comparator by instant synchronization pattern omission generated from disc defection. IREF is the reference current input used to determine the current of the TLC and LPF charge pumps, the operating point of the HF comparator, and the VCO free run frequency. If IREF is connected to a noisy power supply through a resistor, VCO would be modulated and the error rate would increase. Therefore, power supply noise at IREF must be held to a minimum.
HPF2
HPF1
TLC
LPF Charge Pump
RC
HF Comparator HF Signal HF defect Signal
SW SW
HF HFD Vref
Charge Pump
Phase Comparator
Charge Pump HF Comparator 3T/11T Detector TLC LPF VCO Reference clock Freq. Comparator Timer
SW
IREF
Current source control
HF Limiter NRZ 1/2 S E L 1/2
LF Limiter 1/2 1/2 VCO
EFM demodulation circuit
Frame Sync Detection Block
Sync loss counter
Fig. 3: EFM - PLL BLOCK DIAGRAM MITSUBISHI ELECTRIC
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(2) Slice level control CHF HF signal RTLC0 RTLC1 RTLC2 HF The slice level control circuit is formed by connecting resistors and capacitors to the HF(High - frequency signal input) and TLC (Slice level control output) pins.
M65827FP
HPF1 HPF1 TLC
(Recommend value) CHF= 0.0022F CTLC= 0.022F RTLC0= 33K RTLC1= 33K RTLC2= 16K Vin= more than 0.5Vp-p
CTLC
(3) PLL circuit Since the adjustment - free VCO is built in, the adjustment - free PLL circuit can be formed by connecting a resistor and capacitors to the LPF(Low Pass Filter) pin. (Recommend value) CLPF= C= RLPF= RPD= 470pF 0.068F 1.8K 560K
LPF RPD CLPF RLPF C
M65827FP
(4) Reference current control Resistors must be connected between the IREF pin and VDD in order to set the reference current used in determining the current values of the TLC pin and LPF pin, the comparator operating current of the slice level control circuit, and VCO free - run frequency. (Recommend value) RIREF= 75K
RIREF
M65827FP
IREF
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(5) VCO frequency gain control The frequency gain of the VCO of the EFM-PLL can be controlled by connecting the external resistor between RC pin and GND. RC
RRC
M65827FP
(Recommend value)
RRC= 15K
Oscillation frequency (Hz)
Oscillation frequency (Hz)
RIREF
RRC
LPF (V)
LPF (V)
The gain of the oscillation frequency (f / V) can be controlled by the external resistor RRC and the minimum oscillation frequency can be controlled by the external resistor RIREF. And the frequency divider ratio of the internal VCO of the EFM-PLL can be also controlled by the address 05h resister for each playback speed. The external resistor RIREF decide the characteristics of the free-run frequency of the internal VCO and the reference current for all analog circuit. If the range of the free run is too wide, the error rate characteristics may be influenced. If the range of the free run is too narrow, the characteristics of the access time may be influenced. And if the minimum oscillation frequency is too high, the low disc rotation detector can not detect less than 2/3 of the normal rotation. So the minimum oscillation frequency need to set less than 1/2 of the play back frequency. The oscillation of the internal VCO of the EFM-PLL can be confirmed at EFFK pin. The oscillation frequency of the VCO of the EFM-PLL = EFFK frequency X 1176 (8.6472MHztyp X S) (7.35KHztyp X S) (S:Play back speed)
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4.EFM demodulation The EFM signal that has been converted to logic level, and the EFM clock that has been extracted from the EFM signal are input to the de-modulator and converted to an 8 bit symbol. The EFM de-modulation depends on the EFM table in the RED book. To demodulate, the demodulator must be synchronized to EFM signal for each frame. The frame synchronization protection circuit holds the synchronization in spire of some lack of synchronization pattern, and prevents false synchronization if demodulator bit-slipping or mis-synchronization occurs. The frame synchronization control block diagram show fig.4.
EFM Edge Detection
Symbol Conversion VCO EFM Timing Generation 23 bit S/R 1/2 1/17 1/35
Sync Detection
1/588 Tfs
Reset Window Signal Generation
Sync
Sync Control Window
Lock Detection
HFD
Sync loss counter
PLL Control
SYCLK
Fig. 4: Frame synchronize control part block diagram In this figure, generation condition of counter reset signal in EFM timing generation block is as follows. Reset = Sync X Tfs + Sync X Window (X: logical multiplication, +: logical addition)
where Sync, Tfs and Window mean synchronization signal, detection signal of synchronization signal blank, and window signal of 7ck. In the synchronous state, Sync and Tfs generate simultaneously and Sync comes to the center of the window. At this time, "H" is output to the SYCLK pin, and EFM signal is synchronized by frame unit. Frame sync. status can be monitored in SYCLK mode at LOCK/DRD pin. On the other hand, the SYCLK signal includes some bounce even during the sync. state when there is a lack of sync. pattern because of a defect in the disc. Hence there is a need for debouncing the sync. status signal, in order for it to be monitored by the MCU. This debouncing is accomplished in the M65827FP by monitoring the frame sync. status at 1/16 EFM frame clock intervals (normal speed: 2.13msec) and then outputting the result to the LOCK/DRD pin. If monitored status is "locked" then output is "H", and after 8 continuous intervals of "unlocked" are observed, output becomes "L". Also, when the disc rotation does not reach the target speed, lock monitor may become "LOCK" state because of its wide lock range. In such state, when an audio disc plays, noise may be generated by releasing mute state when LOCK signal become "H". The LOCK signal can output when the disc rotation in CLV mode in order to prevent noise generation. Output condition of the LOCK signal can be set by the D5 bit of address 07h.
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5.CLV servo control (1) PWM control CLV servo control circuit operates using two signals. The first is the frequency difference between EFM clock and X'tal clock, and the second is the phase difference between write frame address and read frame address of the internal RAM. Motor control signals are output in PWM wave form to the PWM1 (-signal) PWM2 (+signal) pins. Because these signals are internally phase compensated, the CLV servo control circuit can be composed easily using current drivers on pins PWM1 and PWM2. Kick pulse, Brake pulse, and Start/Stop are output to PWM1 and PWM2 under MCU control. When HDF becomes "H" (when HF signal is detected), PWM1 and PWM2 are automatically fixed duty pulse width to prevent disc from overrun. When the difference between the writing address and reading address of internal RAM exceeds 8 frames because of PLL disc rotation jitter, the address of crystal is loaded to PLL address counter and reset so that the jitter margin become maximum. The result of memory overflow from disc rotation jitter can be monitored from the INT pin. The result is expanded to 128 frames. PLL Address Reset 128 Frames Timer Phase Compensation HFD
X'tal Address (Reading Address) PLL Address (Writing Address) Crystal Clock PLL Clock
Phase Comparator + Frequency Comparator Kick
8 frames Detection
INT
Disc Control Brake
PWM
PWM1 PWM2
Start/Stop
Kick Timer
Brake Timer MCU I/F
S/S Control Fig. 5: CLV block diagram
Pin
MODE
KICK H L
CLV
BRAKE L H
STOP L L
PWM2 (+signal) PWM1 (- signal)
* *
Table 3: PWM output state at each mode
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Fig.6 shows CLV wave form and its duty. Disc motor can be driven by PWM waveforms directly, or it can be driven by an analog signal that can be generated by integration of the PWM waveforms. By using an analog signal, it is possible to adjust the servo loop gain by varying direct external component values, but in the case of PWM waveforms, the servo loop gain is determined by motor torque, and the rotating moment of the disc, turntable, and disc clamper.
22.7 / S sec PWM2 PWM1 2 / S sec 2 / S sec (S:PlayBack Speed)
Duty =
WPWM2-WPWM1 WPWM2+WPWM1 +1
+1 -8 frames 8 frames -1 1/2 frame
Fig. 6: CLV waveform
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6. HFD (HF defect signal input) Inputting "H" to the HFD pin when an HF signal defect is detected prevents the PLL and disc from incorrect behavior caused by scratches and dust and fastens PLL re-lock after HF signal recovery. It enable by inputting "H" to HFD input pin when HF signal defect. Internal function is as follows: Internal action when HFD is "H" (1) Charge pump both PLL phase comparator and frequency comparator is HiZ state, VCO control voltage is held (2) Slice level of TLC pin is held (3) CLV PWM output is fixed duty Described function can be canceled by inputting "H" to HFDDIS register at address 01h.
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7.Error correction (1) Correctability Max C1:2 error correction, C2:4 error correction. C1:2 error correction, C2:2 error correction (no eraser correction mode) can be chose at address 01h. (2) Error monitor output Error states which are detected during decoding are output to EST pin by setting ERM register at address D7h. When ERM2, ERM1, and ERM0 are all "0", the error flag is output to the EST pin. On the other case, the unit error flag is output in current frame unit.. CD-ROM mode is selected by the NONAUDIO register at address 01h, output data is not interpolated, and error status of the C2 decoder are output in every data byte that can not be corrected. When the NONAUDIO register at address01h selects audio mode, every interpolating word (2 byte) outputs the error status of the C2 decoder. (a) Frame unit error monitor output (except ERM2=ERM1=ERM0=L) Frame EST Frame which error is detected (b) Data unit error monitor output (b-1) Audio mode (NONAUDIO register is "0") LRCK EST DADT ROMDT Interpolated word Both DADT and ROMDT are same output. (b-2) CD-ROM mode (NONAUDIO register is "1") LRCK EST ROMDT Data with a error DADT ROMDT pin output CD-ROM data. DADT pin output mute data. The frame unit error monitor is a mode to check decode condition. When an error flag is used for CD-ROM decoder, it needs to set ERM register at address 07h to ERM2=ERM1=ERM0=L. Data with a error L (Mute data) Data with a error
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(3) Interpolation When an error word is judged uncorrectable by C2 decoding, average interpolation or pre-hold interpolation is performed and noise product prevented. When an error is detected in a word, if the previous and subsequent words are error-free, average interpolation is attempted. If the previous or subsequent word is in error, pre-hold is tried. When CD-ROM mode is selected by the NONAUDIO register at address 01h, interpolation management is not performed. LRCK EST L D0 R L R X L R L R X L X R X L X R X L X R L R L R L
Average Interpolation
Pre-hold
Average Interpolation
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8.Digital audio interface output The digital audio interface signal according to EIAJ regulation CP-1201 "digital audio interface" is output to the DOTX pin. Validity flag is set automatically to "1" when the interpolated word is transmitted. The data that is read from the subcode interface block is transmitted to user data. Channel status clock accuracy and source number can be set using the MCU interface.
Audio Data
Shift Register 16 Shift Register
Preamble Generator
Bi-phase Mark Modulation
DOTX
CUV
Parity Generator EST
Timing Generator
Source No. Clock Accuracy (MCU I/F)
Channel Status Register
Shift Register 7 SBCQ~W
Fig. 7: Digital out block diagram
Parity bit B: L-channel, the head of blocks M: L-channel, not the head of blocks W: R-channel SYNC AUX Extended bit Audio DATA Channel status User data Validity flag V U C P
4 bit
4 bit "0"
4 bit
LSB
16 bit
MSB
1
1
1
1
Sub frame format Subframe Subframe W R-channel M L-channel Frame 1
M
L-channel
W
R-channel
B
L-channel
Frame 191 Frame format
Frame 0
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Source Coding
Channel Coding (Bi-phase mark)
0
1
0
0
1
1
0
1
0
1
1
0
0
Channel coding (Bi-phase mark modulation) In order to prevent radiation when digital output is not used, DOTX pin output can be fixed to "L" by setting at address 0Fh. Channel status is set in IC as follows:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
16 32 48 64 80 96 112 128 144 160 176
0
from Subcode Q
ID1 COPY EMP
0 0
0 0
0 0
0 0
1 0
0 0
0 0
0 0
0
0
0 0
0 0
SOURCE0 SOURCE1 SOURCE2 SOURCE3
ACCK0 ACCK1
Set by MCU
ALL 0
ID1,COPY,EMP are set when CRC flag is OK and subcode sync S0,S1 are detected at fixed position. In case any condition is NG, previous data is held. The validity flag is copied with the EST flag at audio mode.
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9.Digital de-emphasis M65827FP has a digital de-emphasis circuit composed of a first order IIR filter. When internal circuit defect emphasis state, a 50 /15 de-emphasis circuit automatically becomes active. When DDEPASS register at address 04h is "1", de-emphasis pass mode is selected. Figure 8 shows the characteristics of internal de-emphasis filter.
0 -5
Gain (dB)
(a) Frequency characteristics
-10 -15 -20
0
5000
10000
Frequency (Hz)
15000
20000
180 150 120 90 60 30 0 -30 -60 -90 -120 -150 -180 0 5000
(b) Phase characteristics
Phase (DEG)
10000
Frequency (Hz)
15000
20000
Frequency 0~18kHz 18~20kHz
Deviation* less than0.2dB less than0.5dB * Gain deviation from imaginary equation as follows: (1+S*15S)/(1+S*50S)
Fig. 8: De-emphasis characteristics
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10.DOscillation circuit and Timing generator (1) Internal oscillation mode The oscillation circuit can be formed by connecting a crystal oscillator, load resistance and load capacitors to pins XI and XO.
M65827FP
XI Rx XO
Oscillator 8.4672MHz 16.9344MHz 33.8688MHz
Cx (cf.) 30pF 15pF 5pF
Rx (cf.) 1M 1M 1M (Recommend value)
Cx
Cx
(2) External clock mode When the system contains a clock, the clock can be input to pin XI via a capacitor without using the crystal oscillator. If the input signal is logic level, the capacitor is not necessary.
M65827FP
XI XO External clock VIL External clock 1000pF VIH AMPLITUDE 2VP-P MIN DVSS DVDD3 MAX
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(3) Clock doubler circuit M65827FP has a clock doubler, double and quad frequency master clock can be generated by composing loop filter at DXLPF pin. Clock doubler is selected at address 05h resister. The gain of the internal VCO of the clock doubler can be controlled by connecting the external resistor RDXRC between DXRC pin and GND. And the minimum frequency is determined by the reference current control resistor RIREF. (Recommend value) RDX CDX1 DXLPF RDX = 1.8K CDX1 = 0.15F CDX2 = 470pF RDXRC = 15K
M65827FP
RDXRC CDX2 DXRC
(4) Clock output M65827FP has various master clock dividers in order to realize many playback speeds. Of the clocks given by master clock divider, system clock and half clock are output from special pin. C423 output half clock of the crystal oscillator. C423 can be used for MCU master clock. S846 and S423 output a clock which is synchronized with the M65827FP internal system clock. S846 and S423 can be used for external digital filter and CD-ROM decoder. When PLCKSEL is 1, system clock of M65827FP will be clock generated by PLL, and the clocks of S846 and S423 are synchronized with the PLL clock. When PLCKSEL is 0, system clock of M65827FP will be clock generated by X'tal, and the clocks of S846 and S423 are synchronized the X'tal clock.
(5) C423 (MCU system clock) C423 pin outputs half clock of oscillator's clock. The clock is independent on playback speed selector and clock doubler. it is used for MCU system clock.
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(6) Clock output timing 1.PLCKSEL = 0,EXSEL = 0,DXSEL = 0 MASTER CLOCK 1/1 1/2 1/3* S846 S423 S846 S423 S846 S423 1/4 1/6 S846 S423 S846 S423 1/8 1/10 1/12 S846 S423 S846 S423 S846 S423 2.PLCKSEL = 0,EXSEL = 0,DXSEL = 1 MASTER CLOCK 1/1 1/2 1/3* S846 S423 S846 S423 S846 S423 1/4 1/6 1/8 S846 S423 S846 S423 S846 S423 S846 S423 1/12 S846 S423 *When 1/3 is selected, output of C846 and S846 is 33% duty.
1/10
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3.PLCKSEL = 1 When PLCKSEL register is 1, S846 has 24 intervals in a frame that do not output clock by 588/576 conversion. Other clock and data that is synchronized with S846 have same interval. (7) Sleep mode
Start Clock doubler unselect. If the clock doubler mode is not selected, this step is not needed. (B) Set "1" at the D2 and D4 bit of address 0Fh Digital sleep mode. The system clock stop to supply to the internal logic and the internal SRAM change to the disable mode. If C423 output signal is used in the sleep condition, please set "1" at the only D2 resister of the address 0Fh. If C423 output signal is not needed, please set "1" at the D2 and D4 resister of the address 05h. Analog sleep mode. The reference current of all analog circuit is stopped.
Set "0" at the D6 bit of address 05h
(A) Set "1" at the D2 bit of address 0Fh
Set "0" at the D0 bit of address 06h
Set "1" at the D0 bit of address CEh
Stop the oscillation of the VCO of the EFM-PLL. The charge pump of the EFM-PLL output "L" and the internal VCO stop the oscillation.
Sleep complete
Start
Set "1" at the D1 bit of address 0Fh
Set "0" at the D1 bit of address 0Fh
DSP is initialized by the hard reset command and the sleep mode is canceled . This command is same with inputting reset pulse to ALCR pin.
Sleep cancel
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4. Playback speed control selector and each clock frequency DXCK C423 S x 96fs S x 96fs S x 96fs S x 64fs S x 48fs S x 32fs S x 24fs S x 19.2fs S x 9.6fs S x 8fs S x 96fs S x 48fs S x 32fs S x 24fs S x 16fs S x 12fs S x 24fs S x 19.2fs S x 16fs S x 9.6fs S x 8fs S x 16fs S x 192fs S x 96fs S x 64fs S x 48fs S x 32fs S x 12fs S x 6fs S x 4.8fs S x 4fs S x 48fs S x 24fs S x 16fs S x 12fs S x 8fs S x 6fs S x 4.8fs S x 4fs S x 16fs S x 8fs S x 24fs S x 12fs S x 32fs S x 16fs S x 96fs S x 96fs S x 96fs S x 96fs S x 96fs S x 96fs S x 48fs S x 48fs S x 48fs S x 48fs S x 48fs S x 48fs S x 48fs S x 48fs S x 48fs S x 24fs S x (1/2)fs S x (1/3)fs S x (1/4)fs S x (1/6)fs S x (1/8)fs S x (1/10)fs S x (1/12)fs S x fs S x (1/2)fs S x (1/3)fs S x (1/4)fs S x (1/6)fs S x (1/8)fs S x (1/10)fs S x (1/12)fs S x 192fs S x 96fs S x fs S x 48fs L L L L L L L L H H H H H H H H L L L L L L L L L L L L L L L L PLCKSEL S846 S423 DSCK LRCK
Master clock L L H H L L H H L L H H L L H H H L H L H L H L H L H L H L H L
CKSEL2 CKSEL1 CKSEL0
S x 192fs
L
S x 192fs
L
S x 192fs
L
S x 192fs
L
S x 192fs
H
S x 192fs
H
S x 192fs
H
S x 192fs
H
S x 96fs
L
S x 96fs
L
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S x 96fs
L
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S x 96fs
L
S x 96fs
H
S x 96fs
H
S x 96fs
H
S x 96fs
H
fs = 44.1kHz,S:Playback speed (S-times)
Master clock CKSEL2 CKSEL1 CKSEL0 DXCK L H H H H H H H H H H H H H H H H S x 48fs S x 48fs S x 48fs S x 24fs S x 16fs typ S x 48fs S x 32fs typ S x 48fs S x 48fs typ S x 48fs S x 64fs typ S x 48fs S x 96fs typ S x 48fs S x 96fs S x 16fs typ S x 8fs typ S x 96fs S x 96fs S x 24fs typ S x 12fs typ S x 6fs typ S x 4fs typ S x 96fs S x 32fs typ S x 16fs typ S x 8fs typ S x 96fs S x 48fs typ S x 96fs S x 64fs typ S x 96fs S x 96fs typ S x 192fs typ S x 96fs typ S x 48fs typ S x fs typ L L L L L L L H H H H H H H H S x 96fs PLCKSEL C423 S846 S423 DSCK LRCK L L L H L H L H L H L H L H L H H L
S x 192fs
L
S x 192fs
L
S x 48fs typ S x 24fs typ S x (1/2)fs typ S x 32fs typ S x 16fs typ S x (1/3)fs typ S x 24fs typ S x 12fs typ S x (1/4)fs typ S x (1/6)fs typ S x (1/8)fs typ S x (1/12)fs typ S x fs typ
S x 192fs
L L L
H
S x 192fs
L
H
S x 192fs
H
S x 192fs
H
S x 192fs
H L L
H
S x 19.2fs typ S x 9.6fs typ S x 4.8fs typ S x (1/10)fs typ S x 192fs typ S x 96fs typ S x 48fs typ
S x 192fs
H
H
S x 96fs
L
S x 96fs
L
S x 48fs typ S x 24fs typ S x (1/2)fs typ S x 32fs typ S x 16fs typ S x (1/3)fs typ S x 24fs typ S x 12fs typ S x (1/4)fs typ S x 16fs typ S x 8fs typ S x 12fs typ S x 6fs typ S x 8fs typ S x 4fs typ S x (1/6)fs typ S x (1/8)fs typ S x (1/12)fs typ
S x 96fs
L L L
H
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S x 96fs
L
H
MITSUBISHI ELECTRIC
S x 96fs
H
S x 96fs
H
S x 96fs
H
H
S x 19.2fs typ S x 9.6fs typ S x 4.8fs typ S x (1/10)fs typ
S x 96fs
H
H
fs = 44.1kHz,S:Playback speed (S-times)
At PLCKSEL=1, C846 and C423 are synchronized to master clock, S846, S423, DSCK, and LRCK are synchronized to PLL. S846, S423, DSCK, and LRCK represent typical state frequency which disc rotation reaches at target playback speed.
APPLICATION CIRCUIT
0.1F 910 2SC710 4.3k 470PF 0.15F 1.8k 0.1F
6 MCK 2 DVDD3 3 DXLPF 4 LOCK/DRD 5 SBQS XI 41 XO 40 EST 39 C423 38 INT 37 1 DVDD5 DVSS 42
33.8688MHz 1M 5PF Error monitor System clock for MCU Interrupt output (to MCU) Track cross signal System clock
M65827FP
7 R/W
TRIN 36 S423 35 S846 34 PWM1 33 PWM2 32 ROMDT 31 DSCK 30 LRCK 29 DADT 28 CRCF 27 DOTX 26 SCCK 25 EFFK 24 SBCO 23 SCAND 22
MCU interface
8 MSD 9 MLA 10 ALCR
Spindle motor control
HFD input 15k 0.068F 1.8k 470PF 0.0022F HF signal 33k 16k 15k 33k 75k
11 HFD 12 DXRC 13 IREF 14 AVDD 15 LPF 16 RC 17 HF 18 HPF1 19 HPF2 20 TLC
DAC I/F (CD-ROM I/F)
Digital audio interface Subcode I/F
0.022F
21 AVSS
(Recommend value)
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